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| L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Preliminary Datasheet LSI Logic's L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) is a highly integrated set-top box control and communication device, combining most of the logic needed for a digital broadcast system (DBS) or cable set-top box onto a single chip. The L64118's embedded 32-bit TinyRISCTM MIPS CPU core provides processing power to support transport and system data, as well as general-purpose system control. The L64118 interfaces directly to LSI Logic's L64704 and L64724 (satellite), and the L64768 (cable) single-chip channel decoders, as well as to the L64105 MPEG-2 A/V decoder. The MPEG-2 transport and system demultiplexer can handle 32 Packet Identifications (PIDs) simultaneously, including audio, video, and generalpurpose data services. It integrates a Digital Video Broadcasting (DVB)compliant descrambler block, substantially increasing the security of the set-top box. The L64118's synchronous External System Bus (EBus) communicates with external peripherals. The L64118 communicates with peripherals through serial, parallel, SmartCard, and infrared ports. Several generalpurpose I/O pins are provided that let system designers expand the system's capabilities. The L64118 supports industry-standard SDRAM memory of up to 16 Mbytes, using 16 and 64 Mbit SDRAMs. The SDRAM interface supports PC66/100-compliant SDRAMS. The L64118 is offered in LSI Logic's 3.3 V G10(R)-p cell-based technology and is packaged in a 256-pin PBGA (IF) package. (R) w w w .d sh ta a 4u et e om .c February 1999 Copyright (c) 1997, 1998 by LSI Logic Corporation. All rights reserved. 1 www..com Figure 1 Typical Set-Top Box Using the L64118 Fast Parallel Port PC Modem GP I/Os Optional 1 Mbyte x 16 SDRAM IR Blaster/ Receiver 2x SmartCards Aux Port IEEE1284 Line Driver 3 x RS232 Line Driver VCXO 27MHz SDRAM 16 Mbyte (max.) 27 MHz 16 SDRAM 1 M x 16 16 Satellite/Cable Tuner In L64724 /L64768 TS L64118 PES L64105 2 2 External System Bus I2C 2 16/32 2 8 Optional FLASH 1 Mbyte x 16 16 2 FLASH 1 Mbyte x 16 Teletext Interface 2 NTSC PAL S-VIDEO L-SPEAKER R-SPEAKER PAL / NTSC Encoder PCM DAC CCIR601VIDEO ACLK PCM-AUDIO The L64118's embedded 32-bit MIPS CPU (TR4101) runs at 54 MHz. The chip's CPU block is 32 bit, while the bus interface to external memory (through the SDRAM controller) is 16 bit. The CPU can run MIPS16 and MIPS32 instructions. The 32-bit operations allow high-performance operation, while 16-bit operations allow for code optimization and memory savings. Since most transport processing and filtering is implemented in hardware, much of the CPU's processing power can be devoted to system processing. 2 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) The L64118 processes the transport data packets in the PID Processing Unit (PPU) according to the MPEG-2 standard draft 13818-1, making Packetized Elementary Stream (PES), Program Specific Information (PSI), Service Information (SI), and Private data available to the system. It also buffers and transfers audio and video PES data packets to the external decoder device. The L64118 interfaces directly to LSI Logic's L64105 MPEG-2 A/V decoder. It outputs demultiplexed audio and video PES streams for processing by the L64105. This decoder's extended channel buffer feature lets you use part of the L64118 SDRAM space to store A/V PES data directed to the L64105. One benefit of this is that it lets you free memory in the L64105 and increases its On-Screen Display (OSD) capability. The L64118 also interfaces directly to LSI Logic's family of single-chip channel decoders (L64704, L64724, and L64768), which allows channel data to be transferred in parallel or serial modes. The L64118 implements an automatic sync locking mechanism with a programmable hysteresis function for reliable locking onto MPEG-2 (0x47) transport packet sync bytes. The External System Bus (EBus) is a general-purpose, 32-bit wide system bus. It is controlled by the L64118 for communication with external components in the system. This bus provides the system designer with an interface that permits the glueless connection of devices such as FLASH, ROMs, and external peripherals. The L64118's peripheral interface blocks let you connect external systems directly to the set-top box. The RS232 ports let you connect a PC, modem, or terminal directly to the chip. The IEEE1284 parallel port lets you connect to fast peripheral devices and transfer filtered transport packets. The IEEE1284 parallel port includes an on-chip DMA controller for expediting data transfers between memory to, and from, the port. The L64118 includes an infrared transmitter (blaster) port for applications such as (remotely) programming a VCR, as well as two independent infrared receiver ports, which can be used to program the set-top box using a remote controller. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 3 The 27 MHz system clock drives the L64118 internal demultiplexer block, as well as most of the peripheral modules. The PLL block generates 54 MHz from the 27 MHz system clock to drive the CPU logic. The L64118 includes four DMA channels (one dedicated to the IEEE1284 port, three independent) that can be used to transfer data between peripheral ports and memory, from one memory location to another, or from memory to an external system device. Features The L64118 provides additional system features for a set-top box application, including: Channel * * * Compliance with ISO/IEC 13818-1 (MPEG-2) Transport specifications Sustained rates up to 90 Mbits/s serial and up to 13.0 Mbytes/s parallel transport stream input interface Direct interface to LSI Logic single-chip channel decoder devices, such as the L64704, the L64768, and the L64724 Demux * PID filtering (32 user-programmable PIDs) - - - Hardware-assisted section filtering for 30 general-purpose PIDs (PSI, SI, and Private) Each filter includes 12 match bytes and 12 mask bytes Each PID can select up to 32 filters simultaneously * * * * * * Support of a Program Clock Reference (PCR) PID CRC32 in parallel to all sections in the filtering process Descrambler core compliant to DVB common scrambling specifications Support for transport-level and PES-level descrambling Seamless support of scrambled and unscrambled data Support of up to 12 pairs of 64-bit keys 4 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) * * * * * * Two 256-byte transport buffers for supporting audio and video PES streams 32 programmable cyclic buffers in SDRAM memory assignable to a PID or section filter index Support for an additional programmable cyclic buffer in SDRAM to post data to adaptation fields Program Clock Reference (PCR) recovery and locking Automatic detecting and switching of audio and video PIDs on splice points Audio oversampling (256 or 384 times oversampling) clock generation CPU and Subsystems * Integration of the CPU system: - - - - - - - - 32-bit TR4101 54 MHz TinyRISC CPU MIPS16 and MIPS-II instruction set compatible Four Kbyte Data (direct mapped) and Eight Kbyte (two-way set associative) instruction cache Basic Bus and Cache Controller unit (BBCC) Multiply/Divide Unit (MDU) Debugger Building Module (DBX) 32-bit Timers and Interrupt Controller In-Circuit Emulator (ICE) port * Two interrupt handling modes: - Interrupt Compatibility mode supports 12 interrupt ports and six main interrupt levels. This mode is compatible with the L64108 interrupt structure. Interrupt Extension mode supports 25 interrupt ports with a software index to each interrupt source. This new mode can reduce interrupt latency. - L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 5 Peripherals * * * * * * * * * * * Programmable audio clock generator for oversampling audio DAC (ACLK) Three RS232 serial I/O channels IEEE1284 parallel interface port (shared with the Aux port) Two ISO7816 SmartCard interfaces Two Infrared (IR) receivers One IR transmitter Auxiliary (Aux) fast input/output port with multiple configurations and settings (shared with the IEEE1284 port) Teletext serial interface port with direct interface to NTSC or PAL encoders I2C-compatible interface port supporting multimaster or slave modes for interfacing to external devices Four DMA channels (one dedicated to IEEE1284 port, three independent) Synchronous extension bus - - - - 32-bit external addressing 8-/16-/32-bit data bus width Multiplexed address/data as well as eight demultiplexed address pins Synchronous to a 27 MHz output clock * * * Up to 47 general-purpose pins Six programmable chip-select output signals (five dedicated and one multiplexed) Enhanced serial I/O for modem use SDRAM Controller * * SDRAM Controller supports 16 and 64 Mbit SDRAM devices SDRAM Controller support for up to 16 Mbytes 6 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) General * * * * * On-chip PLL (54 MHz) with internal loop filter JTAG support 256-pin Plastic Ball Grid Array (PBGA) Package Commercial temperature range 0 C-70 C ambient Low-power, 3.3 V ( 10%) process Architectural Overview The components of the L64118 are integrated to provide a complete system solution for demultiplexing and processing incoming MPEG-2 Transport Stream packets. Figure 2 shows the three main blocks of the L64118: the TR4101 CPU and associated core building blocks, the transport (demultiplexer) block, and the peripheral device interfaces. Additionally, the L64118 has three main buses: * Basic Bus (BBus) The BBus is an internal 32-bit bus that connects the CPU core and building blocks with internal memory and peripherals through the CPU-to-Peripheral (C2P) bridge. * Peripheral Bus (PBus) The PBus is the internal peripheral bus; it links the CPU to SDRAM memory, internal peripheral devices, and the demultiplexer using the C2P bridge. * External System Bus (EBus) The EBus is a general-purpose 16- and 32-bit synchronous system bus that lets the L64118 communicate with external components in the system. The EBus connects to the BBus through the EBus controller. The following subsections provide an overview of the chip's main blocks. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 7 Figure 2 L64118 Internal Block Diagram TR4101 TinyRISC Core Bus Controller Cache Controller BBus Cache C2P Interrupt Controller EBus Controller Timers External System Bus DBX MDU Transport Stream CPU Block PBus Internal Peripheral Bus (PBus) ICEport 1284 Parallel Port DMA Controller Aux Parallel Port IR Port Transport Block Register File Channel Decoder Interface Descrambler PID Processor Dispatcher 3 Serial Ports VCx0 27 MHz PCR Clock Recovery SDRAM Controller SDRAM Bus I2CCompatible Interface Teletext Interface SmartCard Interface Peripherals Audio Clock Generator ACLK Video PES Buffer Audio PES Buffer Video Audio PES L64105 Interface 8 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) TinyRISC MIPS CPU Core With its powerful MIPS CPU, the L64118 can support all of the system's general-purpose control requirements, including: * * * * * * Complete set-top system initialization and testing Security handling Communication ports protocol processing Remote control handling PCR recovery and locking Audio/video synchronization for lip-syncing The CPU also supports transport and system data software processing on data posted to the SDRAM by the transport processing block. This includes operations such as: * PSI and DVB SI table maintenance (Program Association Table (PAT), Conditional Access Table (CAT), Program Map Table (PMT), Network Information Table (NIT)) Private Section filtering Subtitle processing and OSD overlay Closed caption and teletext Electronic Program Guide * * * * The MIPS CPU in the L64118 has more than enough processing power to implement all the tasks listed above. The CPU core can be programmed with 16- or 32-bit instructions. The 32-bit operations allow high-performance operation; using the 16-bit architecture permits a reduced code size, saving memory. Both 16- and 32-bit instructions can be used in the same design. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 9 The L64118's TR4101 MIPS CPU is part of LSI Logic's CoreWare(R) technology. The chip integrates the complete CPU subsystem, including: * * * * * * * * * CPU (TR4101) Cache memory for instruction (2 x 4 Kbyte) and data (4 Kbyte) cache Basic BIU and Cache Controller (BBCC) Timers (including watchdog timer) Interrupt Controller Debugger Building Module (DBX) Multiply/Divide Unit (MDU) ICE port (full-duplex, serial receive and transmit port) CPU-to-Peripheral bus (C2P) The L64118's embedded 32-bit MIPS CPU runs at 54 MHz. This clock rate permits a peak processing rate of 54 MIPS. The chip's internal CPU core is implemented in 32-bit architecture, but it can execute both 16-bit and 32-bit instructions. The L64118 has a 16-bit data interface to external SDRAM, and a 32-bit data interface to the external system bus (EBus). The CPU operates in Big Endian1 mode. Since most transport processing and filtering is implemented in hardware, much of the CPU's processing power can be devoted to system processing. The chip includes address decoding logic for directly interfacing to external memory (FLASH, SDRAM) without requiring external glue logic. The interface between the CPU subsystem and the rest of the L64118 is implemented by the C2P unit. The C2P module translates 32-bit data accesses by the CPU to 8- and 16-bit data accesses on the Peripheral Bus, which connects all other blocks. The PBus is synchronous to the 27 MHz system clock. Transport Demultiplexer Block The transport demultiplexer block processes the transport stream data coming from the channel interface. The input of the L64118 transport block interfaces to the channel decoder; the output interfaces to the 1. Big-Endian means that the address of a multiple-byte data type is the address of its most significant byte. 10 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) SDRAM controller module. The block includes a PID processor unit (PPU) that is compliant with DVB and JSAT and meets the requirements of many other service providers, including Canal+, SkyPerfect, and BSkyB. The unit can process up to 32 PIDs simultaneously. It provides extensive filtering of PSI, SI, and Private Sections. The PSI, SI, and Private Sections are filtered according to 32 user-programmable match/mask PIDs. Section data that passes filtering is stored in cyclic buffers (in offchip memory) associated with each PID. Each section in each PID can be filtered against 32 filters. (Every section undergoes a CRC32 check. An enable bit controls the CRC checking of all section types.) The onchip descrambler unit increases system security. The audio and video data are reduced to PES streams and delivered to the A/V decoder. SDRAM Controller The SDRAM controller and resource arbitration logic makes efficient use of SDRAM bandwidth. This chip's low-cost system implementation approach dictates usage of the external SDRAM for both transport and general system functions. The L64118 supports various SDRAM configurations using 16 Mbit and 64 Mbit devices, for a total memory size of 2, 8, or 16 Mbytes of external SDRAM. The SDRAM controller arbitrates access to the external SDRAM. This logic provides the maximum possible SDRAM bandwidth to the on-chip CPU without increasing the need for buffers or other resources. External System Bus (EBus) The External System Bus is a general-purpose 16- and 32-bit system bus used for communication with external components in the system. This bus provides the system designer with an interface that permits the glueless connection of devices like FLASH, ROMs, and external peripherals. The EBus comprises a 32-bit wide interface with multiplexed address and data. Eight address bits are available as demultiplexed bits for easy interface to devices that do not need the full address space. In addition a demultiplexed mode can be configured to provide a 24-bit address and 16-bit data bus. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 11 The EBus controller registers let the user program customized timing for each address space used in a given system. Six address spaces are supported, each with a dedicated chip select output. The main features of the EBus are: * * * * 32-bit physical addressing space 32-bit data width Synchronized to 27 MHz clock Five external interrupt ports The EBus supports the following main signals: * * * * * * * * * 32-bit multiplexed address/data 8-bit demultiplexed (low order) address bits RDn WRn EACKn ALE (Address latch enable) Five dedicated chip-selects and one multiplexed (with memory strobe) chip select 4-bit byte enable bus 27 MHz output clock Peripherals The L64118 integrates several serial and parallel ports, providing a high degree of connectivity to various types of peripherals. The communication ports include: * Three 8251 RS232 serial communication ports connect the set-top box to a dumb monitor, modem, or PC. The modem communicates between the subscriber and the main station, or back channel. One serial I/O includes a V24-compatible UART for a glueless connection to modem datapump ICs. 12 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) * One IEEE1284 parallel communication port for fast communication with a PC or workstation. The L64118 includes an on-chip DMA controller dedicated for data transfers between the IEEE1284 parallel communication port and the main memory. One I2C-compatible serial communication port to communicate with devices using I2C data links. This type of bus is common in video encoders, audio DACs, remote control devices, and RF tuners. Two independent SmartCard ports ISO-7816-3 compliant SmartCard ports interface through a SmartCard coupler, and support the T = 0, T = 1 asynchronous protocol. The ports also feature VCC, VPP control. One Teletext port that interfaces to an NTSC or PAL encoder and allows for direct insertion of teletext data into an NTSC or PAL video encoder device. The teletext data usually is transmitted using a special-purpose PID. The data is then extracted by the Transport processor and posted to SDRAM. Finally, the L64118 controller transfers the teletext data to the Teletext port upon request from the video encoder device. The Teletext port includes a FIFO between the real-time timing required on the output pins and the internal data transfer. An Aux parallel port for outputting/inputting transport packets from/to the internal demultiplexer. The port's direction is controlled through a configuration bit or through the AUXTX input pin. The port can be programmed to deliver or receive transport packets at various points within the demultiplexer's pipeline. This port is multiplexed with signals from the IEEE1284 port. An Infrared port with a single IR blaster with two identical output pins and two identical, yet independent, IR receiver modules. The IRT (transmitter) can be used to communicate with off-board elements (e.g., to program a VCR). The two IR receivers, IR0 and IR1, support remote control of the STB. Forty-seven general-purpose I/O pins (GPIOs) are configurable and can be used to control and monitor a subset of processor functions, thus easing system integration and minimizing external glue logic. Forty-one of these I/Os are multiplexed, six are dedicated GPIOs. * * * * * * L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 13 DMA Controller The L64118 integrates a four-channel DMA controller that reduces a major portion of the load the CPU might incur during data transfer between peripheral ports, memory, and elements residing on the EBus. One DMA channel is dedicated for data transfers between the IEEE1284 port and main memory. The other three DMA channels are generalpurpose. One general-purpose DMA channel (Channel #1) supports transfers between PBus and Ebus devices. In typical applications, one DMA channel can be assigned to a SmartCard, one channel to a serial port, and one to memory to memory data transfers. Addressing The MIPS architecture uses two types of addresses: virtual addresses (used in a program), and physical addresses (that appear on an address bus). This allows support of kernel and user modes, while combining cacheable and noncacheable addresses. Virtual addresses are partitioned into four, fixed-size segments: kuseg, kseg0, kseg1, and kseg2, according to Table 1. Table 1 Memory Segment Address Mapping Segment kuseg kseg0 (cache) kseg1 (noncache) kseg2 (not used) Size 2 Gbytes 512 Mbytes 512 Mbytes 1 Gbytes Virtual CPU Address [31:29] 0b000-0b011 0b100 0b101 0b110-0b111 The kuseg addresses are accessible in user and kernel mode; they are for use by user-mode programs, while also providing direct access (requiring no system call) to those same addresses in kernel mode. Because the L64118 does not have a Memory Management Unit (MMU), kuseg addresses are mapped unchanged to physical addresses. The L64118 does not map kseg2; thus, kseg2 addresses cannot be used by 14 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) the programmer. Noncacheable kseg1 addresses are used for accessing peripheral registers and for code that requires noncacheability (for example, initialization code that is executed before the caches have been flushed). Cacheable kseg0 addresses are used for all other code. The on-chip CPU performs virtual to physical address translation; the resultant 32-bit physical addresses are output on the internal BBus. The CPU to Peripheral (C2P) bridge module maps the 32-bit BBus address to the internal 24-bit PBus address. The EBus interface module (which resides on the internal BBus) maps the 32-bit BBus address to the 24/321-bit EBus address, according to the mode in which the EBus interface is configured and the width of the area being accessed. The L64118 supports a 16 or 32 Mbyte physical address space (depending on the size of the SDRAM supported in the system). Virtual addresses in kseg0 and kseg1 are always mapped to the same physical addresses, namely to the lowest 16 (or 32) Mbytes of physical memory. The programmer can differentiate between cacheable and noncacheable addresses by using a virtual address either in kseg0 or kseg1 (e.g., PSI/PES data is stored in a noncacheable location, since they are posted by the PID processor). As part of the CPU subsystem, the L64118 a small module (the MMU Stub) that maps the kseg0 and kseg1 segments to the same physical address. It does this by clearing the three most significant bits of the address in the kseg0 and kseg1 segments presented by the CPU (on the internal CPU bus). Segments kuseg and kseg2 are unaffected by the MMU Stub. Note that the L64118 CPU operates only in Big-Endian mode; the Ebus must be set to operate in Big-Endian mode. A strap option on the GPIO[42] pin (sampled during reset) determines the physical connection on the EBus. 1. The EBus uses either a 24-bit address or a 32-bit address, depending on the address space being accessed. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 15 The address space of the L64118 is partitioned into the following areas: * CPU/Peripheral This address space contains the control and status registers for the CPU and core building blocks. Configuration Register Space The space contains registers that define the configuration of each peripheral on the PBus. It is partitioned into 1 Kbyte segments, where each segment corresponds to the Configuration register entry for each PBus component. See Table 3. Attribute Register Space The Attribute register space contains the Attribute register 0 for each peripheral on the PBus. This space is partitioned into 1 Kbyte segments, where each segment corresponds to the Attribute register entry for each PBus component. See Table 3. Internal I/O The internal I/O space contains I/O registers and functions for each peripheral on the PBus. It is partitioned into 256 4 Kbyte segments, where each segment corresponds to an I/O entry for a PBus component. See Table 3. External ROM External ROM contains the operating system, user's application programs (kseg0), configuration code, and initialized data (kseg1). External space for the EBus The external space is used for user-defined external memory and external devices residing on the EBus. It is divided into three subspaces, each one supporting devices with a different width (8, 16, 32 bits). * * * * * * Primary SDRAM The lowest 2/8/16 Mbytes of addressable space are mapped to the external SDRAM through the internal SDRAM controller. See Table 2, "PBus to EBus Address Mapping," 16 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Table 2 : PBus to EBus Address Mapping PBus Address 0x0000.0000-0x1F.FFFF 0x0100.0000-0x017F.FFFF 0x0100.0000-0x01FF.FFFF 118 EBus 2 Mbytes SDRAM 8 Mbytes SDRAM 16 Mbytes SDRAM Note that the PBus addresses are not driven on the EBus, but rather are routed to the SDRAM controller. The two Mbyte and eight Mbyte mode are software compatible with the L64108 code, since the External Space 2 (ES2) of the L64108 is located at PBus address 0x0080.0000 (by default). Table 3 summarizes the L64118 address space. Table 3 L64118 Address Mapping PBus/EBus Physical Base Address Not used Not used 0xF4.0000 (PBus) 0xF0.0000 (PBus) 0xE0.0000 (PBus) 0xC0.0000 (EBus demux mode) 0x00.0000 (EBus demux mode)3 0x00.0000 (EBus demux mode)5 0x1000.0000 (EBus mux mode)7 Virtual CPU Base Address Noncache kseg1 0xBFFF.0000 0xBFF8.0000 0xBFF4.0000 Cache kseg0 N/A N/A N/A BBus Base Address 0x1FFF.0000 0x1FF8.0000 0x1FF4.0000 Address Space Name CPU/Peripheral (Reserved1) Not used Internal Configuration Registers Internal Attribute Registers Internal I/O External ROM Size (Mbytes) 0.50 0.50 0.25 0xBFF0.0000 0xBFE0.0000 0xBFC0.0000 N/A N/A 0x9FC0.0000 0x1FF0.0000 0x1FE0.0000 0x1FC0.0000 0.25 1 2 0xB800.00002 0x9800.0000 0x1800.0000 8-bit devices in the External Space 16-bit devices in the External Space 32-bit devices in the External Space 64 0xB400.00004 0x9400.0000 0x1400.0000 64 0xB000.00006 0x9000.0000 0x1000.0000 64 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 17 Table 3 L64118 Address Mapping (Cont.) PBus/EBus Physical Base Address 0x0000.0000 (PBus) 0x0100.0000 (PBus) Virtual CPU Base Address Noncache kseg1 0xA000.0000 Cache kseg0 0x8000.0000 BBus Base Address 0x0000.0000 Address Space Name Primary SDRAM when 2 Mbytes of SDRAM is used Primary SDRAM when 8 or 16 Mbytes of SDRAM is used Size (Mbytes) 2 0xA000.0000 0x8000.0000 0x0000.0000 8 or 16 1. These transactions do not appear on the PBus. This space is used only when the CPU accesses BBus components (BBCC, Timer, C2P, INTC, ICEport). 2. Within this range, used for 8-bit devices, specific address ranges can be selected (and the mode in which they are accessed) using the Ebus address compare registers. 3. Bits [23:0] of the BBus address are reflected onto the EBus Address bus for eight-bit devices. 4. Within this range used for 16-bit devices, specific address ranges can be selected (and the mode in which they are accessed) using the EBus Address Compare registers. 5. Bits [23:0] of the BBus address are reflected onto the EBus Address bus for 16-bit devices. 6. Within this range used for 32-bit devices, specific address ranges can be selected (and the mode in which they are accessed) using the EBus Address Compare registers. 7. Same address used on the EBus and BBus when 32-bit devices are accessed. Signals This section describes the signals used by the L64118. Figure 3 shows the L64118 non-GPIO mode signals in functional groups and Figure 4 shows the L64118 GPIO mode signals. The signals are described by group. Within each group, signals are listed in alphabetic order. 18 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Figure 3 L64118 I/O Signal Summary (Non-GPIO Modes) SA[11:0] SBA[1:0] SBD[15:0] SCASn SDCLK SDQMH SDQML SRASn SWEn AREQn AVALID AVD[7:0] AVERRn VREQn VVALID ACLK AVDD AVSS IREF SC0_C4 SC0_C8 SC0_CLK SC0_DETECT SC0_I/O SC0_RSTn SC0_VCC_ENn SC0_VPP_ENn SC1_CLK SC1_DETECT SC1_I/O SC1_RSTn SC1_VCC_ENn SC1_VPP_ENn CCLK Channel Interface CDATA[7:0] CERRn CVALID SCLK MPEG (PCR) SDET Phase-Locked Loop Infrared Port PLLVDD PLLVSS IRBL IRRX0 IRRX1 IRTX SDRAM Interface External System Bus AD[31:0] ADDR[7:0] ALE BEn[3:0] CPU_CLK CSn[4:0] CSn[5]/MEMSTBn EACKn INTn[4:0] RDn WRn ECLK IDDTN ZTESTn CTSn0 CTSn1/ICECLK DSRn0 DTRn0 RCLK RTSn0 RTSn1 RXD0 RXD1/ICE_RX RXD2 TCLK TXD0 TXD1/ICE_TX TXD2 SCL SDA Audio/Video Decoder Port Audio Clock Generator L64118 I/O Pin Symbol SmartCard0 Port Test Signals SmartCard1 Port Serial Port/ ICEPort I2C-compatible Port Teletext Port TCK TDI IEEE1149.1 TDO JTAG Port TMS TRSTn ACKn/AUXNM AUTOFDn/AUXV BUSY/AUXSB FAULTn/AUXCLK INITn/AUXPID[2] IEEE 1284 Parallel PDATA[7:0] and Auxiliary Port PERROR/AUXPID[0] SELECT/AUXPID[1] SELECTINn/AUX_ADP/AUX_ERR STROBEn/AUX_TX PDATA_DIR/OP_MODE[2] OP_MODE[1:0] RESETn Miscellaneous TTXDATA TTXREQ GPIO[49:48,46:45,43:42] General-Purpose I/Os L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 19 Figure 4 L64118 I/O Signal Summary (GPIO Mode) SA[11:0] SBA[1:0] SBD[15:0] SCASn SDCLK GPIO6 SDQML SRASn SWEn AREQn AVALID AVD[7:0] AVERRn VREQn VVALID ACLK AVDD AVSS IREF L64118 I/O Pin Symbol SC0_C4 SC0_C8 GPIO33 GPIO31 SC0_I/O GPIO30 GPIO32 GPIO34 GPIO38 GPIO36 SC1_I/O GPIO35 GPIO37 GPIO39 TCK TDI TDO TMS TRSTn ACKn/AUXNM GPIO14 GPIO15 GPIO24 GPIO25 GPIO[23:16] GPIO26 GPIO27 GPIO28 GPIO29 CCLK Channel Interface CDATA[7:0] CERRn CVALID SCLK MPEG (PCR) SDET Phase-Locked Loop Infrared Port PLLVDD PLLVSS GPIO47 GPIO40 GPIO41 GPIO44 SDRAM Interface AD[31:0] ADDR[7:0] ALE BEn[1:0] GPIO[3:2] CPU_CLK External System CSn[3:0] Bus GPIO1 CSn[5]/MEMSTBn EACKn INTn[4:0] RDn WRn ECLK Test IDDTN Signals ZTESTn GPIO7 CTSn1/ICECLK GPIO9 GPIO8 RCLK GPIO10 RTSn1 GPIO11 Serial Port/ ICEPort RXD1/ICE_RX RXD2 TCLK TXD0 TXD1/ICE_TX TXD2 I2C-compatible Port Teletext Port SCL SDA Audio/Video Decoder Port Audio Clock Generator SmartCard0 Port SmartCard1 Port IEEE1149.1 JTAG Port IEEE 1284 Parallel and Auxiliary Port GPIO13 GPIO12 GPIO[49:48,46:45,43:42] General-Purpose I/Os PDATA_DIR/OP_MODE[2] OP_MODE[1:0] RESETn Miscellaneous 20 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Table 4 lists the default values of the output and bidirectional signals. Note that during reset, all bidirectional signals (and some output signals) are floating. Table 4 Default Values for L64118 Output and Bidirectional Signals After Reset1 Default Value not asserted inactive (LOW) driving an unknown value driving an unknown value not asserted not asserted not asserted driving an unknown value not asserted not asserted not asserted not asserted not asserted not asserted not asserted floating not asserted not asserted drives assertion floating not asserted Notes Signal ACKn/AUXNM ACLK AD[31:0] ADDR[7:0] ALE AUTOFDn/AUXV AVALID AVD[7:0] AVERRn BEn[3:0] BUSY/AUXSB CSn[4:0] CSn[5]/MEMSTBn DTRn0 FAULTn/AUXSB GPIO42, 43, 45, 46, 48, 49 INITn/AUXPID[0] IRTX PDATA_DIR/ OP_MODE[2] PDATA[7:0] RDn L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 21 Table 4 Default Values for L64118 Output and Bidirectional Signals After Reset1 (Cont.) Default Value not asserted driving an unknown value driving an unknown value floating pulled up by an external pull-up resistor not asserted not asserted floating pulled up by an external pull-up resistor not asserted not asserted not asserted pulled up using an external pull-up resistor pulled up using an external pull-up resistor toggling not asserted not asserted not asserted not asserted serves as an input Notes Signal RTSn0/1 SA[11:0] SBA[1:0] SBD[15:0] SC0_C4, SC0_C8 SCASn SCx_CLK SCx_DETECT SCx_IO SCx_RSTn SCx_VPP_ENn SCx_VCC_ENn SCL SDA SDCLK SDQMH SDQML SRASn SWEn 22 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Table 4 Default Values for L64118 Output and Bidirectional Signals After Reset1 (Cont.) Default Value floating not asserted asserted Notes behaves as an input Signal TTXREQ/GPIO12 TTXDATA TXD0/2 TXD1/ICE_TX VVALID WRn not asserted not asserted 1. A few cycles after reset (RESETn is driven HIGH), the L64118 initiates a transaction on the EBus, changing some of the default values in this table. Channel Interface Port These signals provide the physical connection to Channel Interface devices, such as LSI Logic's L64724 or L64768. This port supports both parallel and serial connections. CCLK Channel Clock Input When CVALID is asserted HIGH, the L64118 latches CDATA[7:0] on the rising edge of CCLK. In serial mode, the L64118 uses only CDATA[0]. In serial mode, the maximum clock rate is 60 MHz; in parallel mode, it is 13 MHz. The CCLK must toggle during reset to ensure proper reset of the channel interface block. Channel Data Input These signals deliver channel information to the L64118. When CVALID is asserted, the chip latches the data on every rising edge of CCLK. When the L64118 is in parallel input mode, all CDATA[7:0] signals deliver data. When the L64118 is in serial mode, only CDATA[0] delivers data. CDATA[7:0] L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 23 CERRn Channel Data Error Input This active LOW input signal indicates that an uncorrected error occurred in the preceding channel interface. When CVALID is asserted, CERRn is latched on the rising edge of CCLK. Channel Data Valid Input This active HIGH input signal indicates that CDATA[7:0] and CERRn are carrying valid data. When CVALID is asserted, a rising edge of CCLK latches the CDATA[7:0] signals into the L64118. CVALID MPEG Program Clock Reference (PCR) Recovery These signals recover the Program Clock Reference (PCR). They interface to the external VCxO, which provides the 27 MHz clock to the decoder. SCLK 27 MHz System Clock Input This input provides the clock signal to the L64118. It must be driven by the external 27 MHz VCxO (the voltage control input is controlled by SDET and the external RC filter). System Clock Sigma-Delta Control Voltage Output This converter output signal from a 16-bit Sigma-Delta modulator inside the L64118 drives a simple low-pass filter to produce an analog control voltage to an external VCxO. SDET Phase-Locked Loop (PLL) These signals supply power and ground to the internal PLL, which generates the internal 54 MHz CPU clock from the external 27 MHz SCLK input. The 54 MHz internal clock is then divided by two to generate the internal 27 MHz clock used by other internal modules. Isolate the PLLVDD and the PLLVSS signals from digital noise and digital logic on the PCB using layout and bypass filtering techniques. PLLVDD PLL Analog VDD Input This provides a separate filtered 3.3 V to the PLL circuit through PLLVDD so that switching noise from the digital portion of the chip can not affect PLL stability. 24 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) PLLVSS PLL Analog VSS Input This provides a separate ground to the PLL circuit through PLLVSS so that switching noise from the digital portion of the chip does not affect PLL stability. External System Bus (EBus) The EBus comprises a 32-bit wide interface with multiplexed address and data. Eight address bits are available as demultiplexed bits for an easy interface to devices that do not need the full address space. All bus transactions are synchronous to the 27 MHz output CPU_CLK. A subset of these signals can be programmed to act as general-purpose I/O signals by setting bit [0] in the General-Purpose Mode register. AD[31:0] Multiplexed Address/Data Bus Bidirectional AD[31:0] is the multiplexed address/data bus. The L64118 can be programmed to drive the full address on this bus at access start. After this address phase the bus presents write data for a write or the external device drives data on the bus in a read. Demuxed Address Bus Output ADDR[7:0] provides eight bits of demultiplexed address bits. This bus allows some designs to remove the external address latch on the multiplexed address/data bus to hold the address throughout the transaction. The EBus uses byte addressing. All 16-bit devices must ignore ADDR[0]. All 32-bit devices must ignore ADDR[1:0]. Address Latch Enable Output This active HIGH signal controls the latches for demultiplexing the address from the AD bus. Byte Enables Output The four byte enable outputs are asserted during a read or write transaction on the EBus to control which of the four byte lanes are enabled. The byte lane selection is dependent on the width of the transaction (word, halfword, or byte) and the data width of the external device (32, 16, or 8 bits). ADDR[7:0] ALE BEn[1:0] L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 25 The byte enables always correspond to the same physical lines on the AD bus: BEn[1] corresponds to AD[15:8], BEn[0] to AD[7:0]. BEn[2] Byte Enable Output The four byte enable outputs are asserted during a read or write transaction on the EBus to control which of the four byte lanes are enabled. The byte lane selection is dependent on the width of the transaction (word, halfword, or byte) and the data width of the external device (32, 16, or 8 bits). The byte enables always correspond to the same physical lines on the AD bus: BEn[2] corresponds to AD[23:16]. GPIO2 Bidirectional BEn[2] can serve as a general-purpose I/O signal (GPIO2) by setting bit 0 in the General-Purpose Mode register. BEn[3] Byte Enable Output The four byte enable outputs are asserted during a read or write transaction on the EBus, to control which of the four byte lanes are enabled. The byte lane selection is dependent on the width of the transaction (word, halfword, or byte) and the data width of the external device (32, 16, or 8 bits). The byte enables always correspond to the same physical lines on the AD bus: BEn[3] corresponds to AD[31:24]. GPIO3 Bidirectional BEn[3] can serve as a general-purpose I/O signal (GPIO4) by setting bit 0 in the General-Purpose Mode register. CPU_CLK EBus Output Clock Output This 27 MHz output clock is generated dividing the on-chip 54 MHz clock by two. This clock serves as the reference signal for all transactions on the EBus. The timing relationship between the SDCLK output clock, the 27 MHz SCLK input and the 27 MHz CPU_CLK output is unknown. 26 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) CSn[3:0] Programmable Chip Selects Output Each chip select pin can be programmed to assert in a specific address area. These pins are used to select specific external devices according to on-chip address decoding. They make interfacing to various peripherals easier, as they can remove the need for external address decoders. Programmable Chip Select Output This pin is similar in function to the other five chip select output pins. It is used to select specific external devices according to on-chip address decoding. GPIO1 Bidirectional CSn[4] can serve as a general-purpose I/O signal (GPIO1) by setting bit 0 in the General-Purpose Mode register. CSn[4] CSn[5]/MEMSTBn Chip Select[5] or Memory Strobe Output This pin is similar in function to the other five chip select output pins but holds the characteristic of being able to function as the MEMSTBn (active LOW memory strobe) signal. The MEMSTBn signal is a general-purpose signal. It can be used to indicate that a memory transaction is in progress. It is asserted in both read and write cycles. The timing on this signal is programmable. EACKn Target Acknowledge Input This signal indicates to the L64118 that the external device is ready to complete the current read or write cycle. The transaction will finish if both EACKn is asserted and the internal wait state generator has expired. This mechanism allows devices to extend an access beyond the number of wait states programmed for that particular address area. EACKn can be programmed to be either active HIGH or LOW, using the XPOS bit in the CEBUSMODE register. EACKn must be deasserted before the next transaction acknowledge cycle. For self-acknowledge devices, the external EACKn pin can be ignored, so the transaction completes when the wait state generator expires. This is controlled by the XACK bit in the CECFGn register. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 27 INTn4 Interrupt Input This unmaskable interrupt can be used for highest priority system needs. Interrupts Input These four external interrupts can be programmed to be level- or edge-triggered sensitive. Interrupts INTn[3:0] are maskable and for general-purpose use. When the L64118 receives an interrupt, the internal CPU completes the execution of the current instruction and jumps to a preprogrammed location in the memory containing the handler for this interrupt. By default, these signals are level triggered after reset. Read Output The active LOW read strobe is asserted during read operations, and deasserted during writes. Write Enable Output The active LOW write strobe is asserted during write operations and deasserted during reads. INTn[3:0] RDn WRn Miscellaneous Signals These general signals are not necessarily associated with a specific function or module of the L64118. OP_MODE[1:0] Operational Mode Input These signals, along with OP_MODE[2], are used as strap options to configure various LSI Logic test modes. For normal operation, configure OP_MODE[2:0] to 0b000. That is, OP_MODE[1:0] should be tied LOW, and OP_MODE[2] should be pulled LOW with a 10 k resistor. OP_MODE[2]/PDATA_DIR Operational Mode Input This signal is used as a strap option during reset in conjunction with the OP_MODE[1:0] pins, and must be pulled LOW with a 10 k resistor for proper device operation. 28 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Parallel Data Direction Output After reset, this signal serves as the PDATA_DIR output, which controls the parallel data bus buffers for the 1284 PDATA[7:0] data lines. When the 1284 port is used as an Aux port, this pin is driven HIGH. RESETn Asynchronous Reset Input Asserting this active LOW signal resets the L64118 to its power on state. To ensure a complete reset of the L64118, RESETn must be asserted for at least 16 SCLK cycles. Test Signals These signals are for LSI Logic test purposes. They must be tied to a constant value in normal operational mode. ECLK IDDTN ZTESTn Connect to VSS This is an LSI Logic manufacturing test pin. Connect to VSS This is an LSI Logic manufacturing test pin. Connect to VDD This is an LSI Logic manufacturing test pin. It is deasserted HIGH for normal chip operation. Input Input Input Serial Port/ICEPort These signals connect the L64118 to an external modem, PC, terminal, or other host that includes an RS232 interface. The L64118 contains three serial ports that comply with the asynchronous specification of the RS232 standard. The on-chip baud rate generators support the standard bit rate for serial communication. Three of the SIO1 signals can be configured to serve the internal ICEport module. CTSn0 Clear to Send Port 0 Input When reset LOW, this signal indicates that the external receiver is ready for data transfer through TxD0/RxD0. If the Transmit Enable bit in the SIO Command register is set HIGH when CTSn0 is reset LOW, data from the Transmit register of Port 0 is serialized through TxD0. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 29 GPIO7 Bidirectional CTSn0 can serve as a general-purpose I/O signal (GPIO7) by setting bit 1 in the General-Purpose Mode register. CTSn1/ICECLK Clear to Send Port1 Input This pin can serve as either the Clear to Send signal of SIO1, or as the ICEport clock input for the ICEport module. The strap option on GPIO[43] controls this pin's functionality and usage. If GPIO[43] is sampled HIGH during reset, this pin serves as CTSn1. When reset LOW, this signal indicates that the external receiver is ready for data transfer through TxD1/RxD1. If the Transmit Enable bit in the SIO Command register is set HIGH when CTSn1 is reset LOW, data from the Transmit register of Port 1 is serialized through TxD1. Serial ICE Clock Input When serial ICE mode is enabled, this pin functions as ICECLK, the synchronous ICE port clock input. DSRn0 Data Set Ready Port 0 Input When reset to LOW, this general-purpose input control signal indicates that an external terminal device is ready for data transfer. The polarity of DSRn0 is latched in Port 0 Status register for the CPU to read. GPIO9 Bidirectional DSRn0 can serve as a general-purpose I/O signal (GPIO9) by setting bit 1 in the General-Purpose Mode register. DTRn0 Data Terminal Ready Port 0 Output When this general-purpose output control signal is reset to LOW, data for the external terminal device is ready to be transmitted. DTRn0 can be set or reset by programming the DTR bit in the SIO Command register. By default, this signal is not asserted after reset. GPIO8 Bidirectional DTRn0 can serve as a general-purpose I/O signal (GPIO8) by setting bit 1 in the General-Purpose Mode register. 30 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) RCLK Receive Serial Data Clock Input This signal is used for the receive clock input in the enhanced UART mode. Request to Send Port 0 Output When this general-purpose, programmable control signal is reset to LOW, Port 1 is ready to send data through TxD1. This signal is set and reset by programming the RTS bit in the SIO Command register. By default, this signal is not asserted after reset. GPIO10 Bidirectional RTSn0 can serve as a general-purpose I/O signal (GPIO10) by setting bit 1 in the General-Purpose Mode register. RTSn0 RTSn1 Request to Send Port1 Output When this general-purpose, programmable control signal is reset to LOW, Port 1 is ready to send data through TxD1. This signal is set and reset by programming the RTS bit in the SIO Command register. Receive Data Port 0 Input This signal provides serial data from an external RS232 device. Its protocol is similar to that of TxD0. The receive baud rate can be programmed in the SIO Baud Rate register. The data received on RXD0 is latched in the Receive register of Port 0. GPIO11 Bidirectional RXD0 can serve as a general-purpose I/O signal (GPIO11) by setting bit 1 in the General-Purpose Mode register. RXD0 RXD1/ICE_RX Receive Data Port 1 Input This pin serves either as the Receive port signal of SIO1, or as the ICEport receive input for the ICEport module. The strap option on GPIO[43] controls this pin's functionality and usage. If GPIO[43] is sampled HIGH during reset, this pin serves as RXD1. In that case, this signal provides serial data from an external RS232 device. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 31 The protocol of this pin is similar to that of TxD1. The receive baud rate is determined by programming the SIO Baud Rate register. The data received on RXD1 is latched in the Receive register of Port 1. If GPIO[43] is sampled LOW during reset, then this pin serves as the receive port for the ICEport in the L64118. Receive Data - Serial ICE Port Input When the serial ICE mode is enabled, this pin functions as ICE_RX, the receive data port input. RXD2 Receive Data Port 2 Input This signal provides serial data from an external RS232 device. The protocol of this pin is similar to that of TxD2. The receive baud rate is determined by programming the SIO Baud Rate register. The data received on RXD2 is latched in the Receive register of Port 2. Transmit Serial Data Clock Input This signal is used for the transmit clock in the enhanced UART mode. Transmit Data Port 0 Output This signal outputs data in compliance with the RS232 protocol's asynchronous specification. The transmit baud rate is determined by programming the SIO Baud Rate register. Data transmitted on TXD0 comes from the Transmit register of Port 0. By default, this signal is not asserted after reset. Transmit Data Port 1 Output This pin can serve as either the Transmit Data port signal of SIO1, or as the ICEport receive input for the ICEport module. The strap option on GPIO[43] controls this pin's functionality and usage. If GPIO[43] is sampled HIGH during reset, this pin serves as TXD1. When set to TXD1, this signal outputs data in compliance with the RS232 protocol's asynchronous specification. The data rate on this pin is determined by programming the SIO Baud Rate register. Data transmitted on TXD1 comes from the Transmit register of Port 1. TCLK TXD0 TXD1/ICE_TX 32 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Transmit Data - Serial ICEPort Output If GPIO[43] is sampled LOW during reset, this pin serves as ICE_TX, the serial ICE transmit data output port. By default, this signal is not asserted after reset. TXD2 Transmit Data Port 2 Output This signal outputs data in compliance with the RS232 protocol's asynchronous specification. The data rate on this pin is determined by programming the SIO Baud Rate register. Data transmitted on TXD2 comes from the Transmit register of Port 2. By default, this signal is not asserted after reset. SDRAM Interface The following group of signals provides the interface between the L64118 and external SDRAM devices. The SDRAM interface works with PC66/100 compliant SDRAMs. The L64118 SDRAM interface runs at 54 MHz and is capable of accessing 2, 4, 8, or 16 Mbyte memory configurations using 16 Mbit or 64 Mbit devices. This interface has a 16-bit data bus (SBD[15:0]). The upper and lower byte mask signals (SDQMH and SDQML) control halfword and byte accesses. The SBA[1:0] outputs support two- and four-bank SDRAM devices. The L64118 automatically performs SDRAM refreshes. The L64118 does not support the Chip Select (CSn) and Clock Enable (CKE) signals. Tie these SDRAM signals active LOW and HIGH, respectively, on the SDRAM device(s) used. SA[11:0] SDRAM Address Bus Output These signals carry the 12-bit SDRAM address bus. The number of row and column address bits used is programmable in the SDRAM Configuration register. SDRAM Bank Select Output These signals allow access to SDRAM devices with either two or four banks. The number of bank select bits used is programmable in the SDRAM Configuration register. SBA[1:0] L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 33 SBD[15:0] SDRAM Data Bus Bidirectional This data bus is driven by the SDRAM during a read operation, and driven by the L64118 during a write operation. It is 3-stated after reset and when there are no memory accesses. Column Address Strobe Output This signal is the active LOW column address strobe. It is used in conjunction with the SRASn and SWEn outputs to form the SDRAM command. SDRAM Clock Output This is the master SDRAM clock. All output signals are referenced to the rising edge of SDCLK. The programmable SDRAM timing parameters are expressed in SDCLK periods. High Byte Mask Output This active HIGH signal is the high byte data mask, which controls the high byte input/output buffer of the external SDRAM. When asserted, it disables (masks) the high data byte of the SDRAM data bus. GPIO6 Bidirectional SDQMH can serve as a general-purpose I/O signal (GPIO6) by setting bit [0] in the General-Purpose Mode register. SCASn SDCLK SDQMH SDQML Low Byte Mask Output This active HIGH signal is the low byte data mask, which controls the low byte input/output buffer of the external SDRAM. When asserted, it disables (masks) the low data byte of the SDRAM data bus. Row Address Strobe Output This signal is the active LOW row address strobe. SRASn is used in conjunction with the SCASn and SWEn outputs to form the SDRAM command. Write Enable Output This signal is the active LOW write enable strobe. SWEn is used in conjunction with the SRASn and SCASn outputs to form the SDRAM command. SRASn SWEn 34 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Audio/Video Decoder Port These signals provide the interface between the L64118 and an external MPEG-2 Audio/Video decoder. This interface supports a seamless connection between the L64118 and LSI Logic's L64105 A/V decoders. It supports a serial data transfer rate up to 27 Mbits/s in serial mode, 9 Mbytes/s in parallel mode. The actual data rate is controlled by the audio and video request signals coming out from the A/V decoder device. AREQn Audio Data Request Input When asserted, this signal indicates that the external A/V decoder is requesting the audio bit to be clocked in to the external A/V decoder. Deassertion of AREQn indicates that the A/V decoder is not ready to accept audio data. Audio Data Valid Output When asserted, this signal indicates that valid audio data is available on the AVD[7:0] bus. A LOW-to-HIGH transition of SCLK causes the audio data bit on AVD to be latched in the external A/V decoder. In serial mode, AVALID is active HIGH. In parallel mode, AVALID latches data on the rising edge. This signal is not asserted after reset. Audio Video Compressed Data Bidirectional This bus provides data to the external A/V decoder. In serial mode, AVD[0] carries the data. In parallel mode, the entire bus carries the byte-wide data. The L64118 outputs PES audio and video data from the on-chip buffers and SDRAM buffers through AVD[7:0]. These signals drive an unknown value after reset. Audio Video Data Error Output When asserted, this signal indicates that there is an uncorrected error in the bit stream entering the external A/V decoder. The L64118 generates AVERRn as a result of detection of discontinuity in the transport packets of the audio and/or video program being decoded. Usually, the discontinuity is the result of loss of packets from uncorrected errors. This signal is not asserted after reset. Video Data Request Input When asserted, this signal indicates that the external A/V decoder device is requesting the video bit to be AVALID AVD[7:0] AVERRn VREQn L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 35 clocked in to the external A/V decoder. Deassertion of VREQn indicates that the A/V decoder is not ready to accept video data. VVALID Video Data Valid Output When asserted, this signal indicates that valid video data is available on the AVD line. The LOW-to-HIGH transition of SCLK causes the video data bit on the AVD[7:0] bus to be latched in the external A/V decoder. In serial mode, VVALID is active HIGH. In parallel mode, VVALID latches data on the rising edge. This signal is not asserted after reset. Audio Clock Generator These signals generate the oversampling audio clock, which drives the L64105 external A/V decoder and a low-cost audio DAC. The audio clock generation circuit provides oversampling audio frequencies locked to the 27 MHz program clock. The fully programmable circuit supports a wide range of oversampling audio frequencies. It is implemented using advanced mixed-signal technology. ACLK Audio Clock Output ACLK provides the oversampling audio clock that drives the L64105 audio clock input and the system clock input pin of conventional stereo audio DAC. This signal is driven LOW after reset. Analog VDD 3.3 V Input AVDD provides the power voltage to the analog circuit of the audio clock generator. It must be isolated from the Digital VDD (DVDD) by a 10 H ferrite insulator. Analog Ground Input AVSS provides the analog ground to the audio clock generator circuit. It should must be isolated from the digital ground supply (DGND). Current Reference This pin must be connected as shown in Figure 5. AVDD AVSS IREF 36 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Figure 5 IREF Connection to RC Devices AVDD 0.1 F 16.9 k 1% IREF AVSS L64118 18 IREF 18-bit DAC DAC Controlled Oscillator FSC_CNTL DCO_DIV REF_DIV 14 16 16 Digital FSC 27 MHz ACLK IEEE 1149.1 (JTAG) Port This group of signals drive the IEEE1149.1 Test Access Port (TAP). TCK TDI TDO TMS Test Clock Input This is the clock pin to sample the JTAG input data. Test Data In This line is for the JTAG input test data. Test Data Out This line is for the JTAG output test data. Input Output Test Mode Select Input This line lets you select between active and JTAG mode. When in JTAG mode, the I/Os are serialized. Active mode is for normal operation. Test Port Reset Input When asserted LOW, this signal resets the internal JTAG controller. It does not reset the chip. TRSTn L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 37 IEEE1284 Parallel Port and Auxiliary Port These signals provide a parallel connection between the L64118 and an external peripheral device. The port complies to IEEE1284 standards and supports several modes. The 1284 mode is enabled when the AUX_SEL bit is reset (System Mode register, bit 4). This port also serves as an auxiliary port for receiving and transmitting transport bitstreams from various points in the on-chip demultiplexer pipeline. The Aux mode is enabled when the AUX_SEL bit is set (System Mode register, bit 4). The following list shows each pin's functionality as an IEEE1284 port and Aux port signal. Some of these pins also can serve as general-purpose I/O pins. ACKn/AUXNM 1284 - Acknowledge Output When the L64118 asserts this signal, valid data is latched in the L64118 IEEE1284 input register. By default, this signal is not asserted after reset. Aux - Aux No Match Output In Aux mode, this signal functions as AUXNM to indicate that the data being sent through the auxiliary port is for a transport packet that failed PID filtering. AUTOFDn/AUXV 1284 - Autofeed Input In 1284 mode, this pin functions as the Autofeed input. Aux - Data Valid Bidirectional In Aux mode, this pin functions as AUXV, which is used as a qualifier indicating that the data presented on the auxiliary data bus is valid. GPIO14 Bidirectional This signal can serve as a general-purpose I/O signal (GPIO14) by setting bit 3 in the General-Purpose Mode register. 38 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) BUSY/AUXSB 1284 - Peripheral Busy Bidirectional In 1284 mode, this signal functions as BUSY. When this signal is HIGH, the 1284 port is not ready for a data transfer. By default, this signal is not asserted after reset. Aux - Sync Byte Bidirectional In Aux mode, this signal functions as AUXSB to indicate that the data being sent through the auxiliary port is the first byte (sync byte) of a transport packet. GPIO15 Bidirectional This signal can serve as a general-purpose I/O signal (GPIO15) by setting bit 3 in the General-Purpose Mode register. FAULTn/AUXCLK 1284 - Peripheral Fault Operation Bidirectional In 1284 mode, this signal functions as FAULTn. This signal indicates that the 1284 port encountered an error during operation. Typically, this error is due to overrun, underrun, or parity error. Aux - Aux Port Clock Bidirectional In Aux mode, this signal functions as AUXCLK, which is the reference clock for all transactions on the auxiliary port. When the Aux port is configured as an output port, this signal is an output with programmable frequencies of 13.5, 6.75 and 3.375 MHz. When the Aux port is configured as an input port, this signal is an input with a frequency based on the input transport stream data rate. GPIO24 Bidirectional This signal can also serve as a general-purpose I/O signal (GPIO24) by setting bit 3 in the General-Purpose Mode register. INIT/AUXPID[2] 1284 - Peripheral Initialization Input In 1284 mode, this signal functions as INITn. When reset LOW, this signal resets the IEEE1284 port and returns the logic to the compatibility and idle state. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 39 Aux - Packet ID [2] Output In Aux mode, this signal is part of a three-bit packet ID that can be assigned to PIDs that are output to the Aux port. GPIO25 Bidirectional This signal can also serve as a general-purpose I/O signal (GPIO25) by setting bit 3 in the General-Purpose Mode register. PDATA[7:0] Parallel I/O Data Signals 1284 Bidirectional In 1284 mode, these signals carry the data transferred between the host and the IEEE1284 port. Aux Bidirectional In Aux mode, PDATA[7:0] carry the transport packets from/to the L64118 demultiplexer and the Aux port. GPIO[23:16] Bidirectional These signals can also serve as a general-purpose I/O bus (GPIO[23:16]) by setting bit 3 in the General-Purpose Mode register. By default, this signal is not asserted after reset. PDATA_DIR/OP_MODE[2] 1284 - Peripheral Data Direction Output After reset, this signal serves as the PDATA_DIR output signal that controls the parallel data bus buffers in 1284 mode. In Aux mode, this pin is driven HIGH. Operational Mode 2 Input This signal is used as a strap option during reset. For normal device operation, use a 10 k to pull this signal LOW during reset. PERROR/AUXPID[0] 1284 - Peripheral Error Output In 1284 mode, this signal functions as PERROR. When HIGH, this signal indicates that the L64118 IEEE1284 port encountered an error during the data processing. FAULTn is asserted whenever PERROR is activated. 40 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Aux - Packet ID [0] Output In Aux mode, this signal is part of a three-bit packet ID that can be assigned to PIDs that are output to the Aux port. GPIO26 Bidirectional This signal can also serve as a general-purpose I/O signal (GPIO26) by setting bit 3 in the General-Purpose Mode register. SELECT/AUXPID[1] 1284 - Peripheral Select Output When set HIGH, this signal indicates that the L64118 IEEE1284 port was selected and is connected to the host. Aux - Packet ID [1] Output In Aux mode, this signal is part of a three-bit packet ID that can be assigned to PIDs that are output to the aux port. GPIO27 Bidirectional This signal can also serve as a general-purpose I/O signal (GPIO27) by setting bit 3 in the General-Purpose Mode register. SELECTINn/AUX_ADP/AUX_ERR 1284 - Peripheral Selection Indicator Input In 1284 mode, this signal (when asserted LOW) indicates that the external host is attempting to select a peripheral. Aux - Adaptation Field Flag Output In Aux output mode, this signal functions as AUX_ADP, which indicates if the output byte is part of an adaptation field. Aux - Error Indicator Input In Aux input mode, this signal functions as AUX_ERR, which indicates if the incoming byte is part of a packet that has an error. GPIO28 Bidirectional This signal can also serve as a general-purpose I/O signal (GPIO28) by setting bit 3 in the General-Purpose Mode register. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 41 STROBEn/AUX_TX 1284 - Data Strobe Input In 1284 mode, this signal functions as STROBEn. When set LOW, this signal indicates that valid data is present on PDATA[7:0]. L64118 latches the data on the rising edge of STROBEn. Aux - Aux Port Direction Input In Aux mode, this signal is used to specify the direction of the aux port if the PINACT bit (bit 4) is set in the Aux Control register. If AUX_TX is HIGH, then the Aux port is an output. If AUX_TX is LOW, then the Aux port is an input. GPIO29 Bidirectional This signal can also serve as a general-purpose I/O signal (GPIO29) by setting bit 3 in the General-Purpose Mode register. I2C-Compatible Port These signals connect the L64118 to an external I2C device. The L64118 uses them to initialize external devices in the system that have this interface. SCL Serial Clock Bidirectional SCL provides the clock signal for transmitting and receiving data through SDA. Serial Data Bidirectional SDA provides the data connection to the I2C-compatible port. Data is transmitted and received through this line according to the I2C protocol. This signal should be pulled HIGH by an external pull-up resistor. SDA 42 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Teletext Port These signals connect the L64118 to an external NTSC/PAL video encoder with a Teletext port. TTXDATA Teletext Data Master Output This signal supplies the teletext data to the external video encoder. The L64118 outputs teletext data when TTXREQ is asserted and there are enough bits in the teletext output buffer to supply one complete teletext line. By default, this signal is not asserted after reset. GPIO13 Bidirectional TTXDATA can serve as a general-purpose I/O signal (GPIO13) by setting bit 2 in the General-Purpose Mode register. TTXREQ Teletext Data Request Master Input When set HIGH, this signal indicates that the external video encoder device requests teletext data to be transferred through TTXDATA. The L64118 outputs teletext data on the TTXDATA pin as long as TTXREQ is asserted. You must program the Video Encoder device so the length of assertion of TTXREQ is compatible with the exact number of teletext bits per line. The L64118 Teletext port supports a direct connection to the Teletext port of NTSC/PAL video encoders. During normal operation, this is an input signal. By default, this signal is not asserted after reset. GPIO12 Bidirectional TTXREQ can serve as a general-purpose I/O signal (GPIO12) by setting bit 2 in the General-Purpose Mode register. SmartCard Port These signals provide the connection between the L64118 and external SmartCard devices. These signals are used by the L64118 to initialize external devices in a system with such a port. The L64118 supports two independent SmartCard devices. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 43 SC0_C4 SmartCard 0 Pin 4 Bidirectional This signal is connected to the C4 pin on the SmartCard. This signal should be pulled up by an external pull-up resistor after reset. SmartCard 0 Pin 8 Bidirectional This signal is connected to the C8 pin on the SmartCard. This signal should be pulled up by an external pull-up resistor after reset. SmartCard 0 Clock Output This signal is the output clock for SmartCard 0. GPIO33 Bidirectional SC0_CLK can serve as a general-purpose I/O signal (GPIO33) by setting bit 4 in the General-Purpose Mode register. By default, this signal is not asserted after reset. SC0_C8 SC0_CLK SC0_DETECT SmartCard 0 Detect Input When HIGH, this signal indicates that a card is inserted in slot 0. GPIO31 Bidirectional SC0_DETECT can serve as a general-purpose I/O signal (GPIO31) by setting bit 4 in the General-Purpose Mode register. By default, this signal floats after reset. SC0_I/O SmartCard 0 I/O Bidirectional This signal transfers data (using the coupler) between SmartCard 0 and the SmartCard port of the L64118. It is open-drain. This signal must be pulled up by an external resistor after reset. SmartCard 0 Reset This signal resets SmartCard 0. Output SC0_RSTn GPIO30 Bidirectional SC0_RSTn can serve as a general-purpose I/O signal (GPIO30) by setting bit 4 in the General-Purpose Mode register. By default, this signal is not asserted after reset. 44 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) SC0_VCC_ENn SmartCard 0 VCC Enable Output This signal turns the power supply of SmartCard 0 on or off. When LOW, it enables the VCC supply. GPIO32 Bidirectional SC0_VCC_ENn can serve as a general-purpose I/O signal (GPIO32) by setting bit 4 in the General-Purpose Mode register. By default, this signal is not asserted after reset. SC0_VPP_ENn SmartCard 0 VPP Enable Output This signal turns the power supply of SmartCard 0 on or off. When LOW, it enables the VCC supply. GPIO34 Bidirectional SC0_VPP_ENn can serve as a general-purpose I/O signal (GPIO34) by setting bit 4 in the General-Purpose Mode register. By default, this signal is not asserted after reset. SC1_CLK SmartCard 1 Clock This signal clocks the output of SmartCard1. Output GPIO38 Bidirectional SC1_CLK can serve as a general-purpose I/O signal (GPIO38) by setting bit 5 in the General-Purpose Mode register. By default, this signal is not asserted after reset. SC1_DETECT SmartCard 1 Detect Input When HIGH, this signal indicates that a card is inserted in slot 1. GPIO36 Bidirectional SC1_CLK can serve as a general-purpose I/O signal (GPIO36) by setting bit 5 in the General-Purpose Mode register. By default, this signal floats after reset. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 45 SC1_I/O SmartCard 1 I/O Bidirectional This signal transfers the data (using the coupler) between SmartCard1 and the SmartCard port of the L64118. It is open-drain. This signal must be pulled up by an external resistor after reset. SmartCard 1 Reset This signal resets SmartCard1. Output SC1_RSTn GPIO35 Bidirectional SC1_RSTn can serve as a general-purpose I/O signal (GPIO35) by setting bit 5 in the General-Purpose Mode register. By default, this signal is not asserted after reset. SC1_VCC_ENn SmartCard 1 VCC Enable Output This signal turns the power supply of SmartCard1 on or off. When LOW, it enables the VCC supply. GPIO37 Bidirectional SC1_VCC_ENn can serve as a general-purpose I/O signal (GPIO37) by setting bit 5 in the General-Purpose Mode register. By default, this signal is not asserted after reset. SC1_VPP_ENn SmartCard 1 VPP Enable Output This signal turns the power supply of SmartCard 0 on or off. When LOW, it enables the VPP pin. GPIO39 Bidirectional SC1_VPP_ENn can serve as a general-purpose I/O signal (GPIO39) by setting bit 4 in the General-Purpose Mode register. By default, this signal is not asserted after reset. 46 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Infrared Port These signals provide the connection between the L64118 and an external infrared receiver and transmitter. IRBL Infrared Blaster Output This signal is the infrared blaster output. This signal can be configured to reflect the value of the infrared transmitter output. GPIO47 Bidirectional IRBL can serve as a general-purpose I/O signal (GPIO47) by setting bit 7 in the General-Purpose Mode register. By default, this signal floats after reset. IRRX0 Infrared Receiver 0 Input This signal serves as the receive port for the demodulated signal of one of the two infrared receivers ports. GPIO40 Bidirectional IRRX0 can serve as a general-purpose I/O signal (GPIO40) by setting bit 7 in the General-Purpose Mode register. By default, this signal floats after reset. IRRX1 Infrared Receiver 1 Input This signal serves as the receive port for the demodulated signal of one of the two infrared receivers ports. GPIO41 Bidirectional IRRX1 can serve as a general-purpose I/O signal (GPIO41) by setting bit 7 in the General-Purpose Mode register. By default, this signal floats after reset. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 47 IRTX Infrared Transmitter Output This signal serves as the infrared transmitter output. GPIO44 Bidirectional IRRX1 can serve as a general-purpose I/O signal (GPIO44) by setting bit 7 in the General-Purpose Mode register. By default, this signal floats after reset. General-Purpose Pins The general-purpose I/O signals for the L64118 let you control and monitor various external events. These signals consist of eight groups. Group 7 contains dedicated GPIO signals, whereas the other groups multiplex the GPIO signals with other functions. Note that all pins within a GPIO group must be enabled or disabled as a group; however, individual GPIO pins can be configured as inputs or outputs using the General-Purpose Control register. The GPIO groups and associated pins are listed in Table 5 through Table 12. Table 5 Pin Name CSn[4] BEn[2] BEn[3] SDQMH Group 1: EBus Signals GPIO Signal1 GPIO1 GPIO2 GPIO4 GPIO6 1. The GPIO3 and GPIO5 signals are not available on the L64118. 48 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Table 6 Pin Name CTSn0 DTRn0 DSRn0 RTSn0 RXDn0 Group 2: SIO Signals GPIO Signal GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 Table 7 Pin Name TTXREQ TTXDATA Group 3: Teletext Signals GPIO Signal GPIO12 GPIO13 Table 8 Pin Name AUTOFDn BUSY PDATA[7:0] FAULTn INITn PERROR SELECT SELECTINn STROBEn Group 4: PIO (IEEE 1284) Signals GPIO Signal GPIO14 GPIO15 GPIO[23:16] GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 49 Table 9 Pin Name SC0_RSTn Group 5: SmartCard 0 Signals GPIO Signal GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 SC0_DETECT SC0_VCC_EN SC0_CLK SC0_VPP_ENn Table 10 Pin Name SC1_RSTn Group 6: SmartCard 1 Signals GPIO Signal GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 SC1_DETECT SC1_VCC_ENn SC1_CLK SC1_VPP_ENn Table 11 Pin Name IRRX0 IRRX1 IRTX IRBL Group 8: Infrared Signals GPIO Signal GPIO[40] GPIO[41] GPIO[44] GPIO[47] 50 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Table 12 Pin Name GPIO[43:42] GPIO[46:45] GPIO[49:48] Group 7: Dedicated GPIO Signals GPIO Signal GPIO[43:42] GPIO[46:45] GPIO[49:48] GPIO[49, 48, 46, 45, 43, 42] Dedicated GPIO Bidirectional These are the dedicated general-purpose I/O signals. By default, these signals float after reset. Note that for LSI Logic manufacturing test purposes, GPIO46 must be pulled HIGH during reset. Programming the General-Purpose Pins To use a general-purpose pin, enable the entire group by writing to the General-Purpose Mode register; then select the input/output for each pin within the group by writing to the specific General-Purpose Control register. (Note that no group has more than 16 general-purpose pins.) After each pin is defined, the programmer can read the value of the GPIO signal using the General-Purpose Data registers, or write the value of a GPIO signal to the General-Purpose Data registers. Latency of GPIO Updates The use of the GPIO pins is intended for controlling/monitoring external logic by the software. You should consider a delay between the time when the software writes a value to a general-purpose output pin and the time the value is valid on the output pin. This delay is caused by the transaction time between the on-chip processor to the on-chip peripheral component, and the delay time of the general-purpose module. The delay that the general-purpose module inserts in writing to an output general-purpose pin is not more than 1 s (for SCLK = 27 MHz). L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 51 When the processor reads a value from a general-purpose pin configured to be an input pin, there is no extra delay inserted; however, the register holding general-purpose input values is updated every 2 s (for SCLK = 27 MHz). Electrical Requirements This section specifies the electrical requirements for the L64118. Five tables list electrical data in the following categories: * * * * * Absolute Maximum Ratings (Table 13) Recommended Operating Conditions (Table 14) Capacitance (Table 15) DC Characteristics (Table 16) Pin Description Summary (Table 17) The following tables provide the maximum ratings, operating conditions, and capacitances for the 3.3 V, G10-p implementation of the L64118. Table 13 Symbol VDD VIN VIN IIN TSTGP Absolute Maximum Ratings Parameter DC Supply 5 V Compatible Input Voltage 3.3 V Input Voltage DC Input Current Storage Temperature Range (Plastic) Limits1 - 0.3 to + 3.9 - 1.0 to 6.0 - 0.8 to 4.7 10 - 40 to + 125 Unit V V V mA C 1. Referenced to VSS. 52 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Table 14 Symbol VDD TA Recommended Operating Conditions Parameter DC Supply Ambient Temperature Limits + 3.0 to + 3.6 0 to + 70 Unit V C Table 15 Symbol CIN COUT CIO Capacitance Parameter1 Input Capacitance Output Capacitance I/O Bus Capacitance Min 5.0 5.0 5.0 Typ - - - Max - - - Units pF pF pF 1. Measurement conditions are VIN = TBD V, TA = 25 C, and clock frequency = 1 MHz. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 53 Table 16 Symbol VIL DC Characteristics Parameter Voltage Input Low TTL CMOS Voltage Input High TTL CMOS 5 V Compatible Voltage Output Low 2-mA Output Buffers 4-mA Output Buffers 6-mA Output Buffers Voltage Output High 2-mA Output Buffers 4-mA Output Buffers 6-mA Output Buffers Current Input Leakage2 with Pulldown with Pullup Current 3-State Output Leakage Current P-Channel Output Short Circuit (4-mA Output Buffers)3, 4 Current N-Channel Output Short Circuit (4-mA Output Buffers)3, 4 Quiescent Supply Current Dynamic Supply Current IOL = 2.0 mA IOL = 4.0 mA IOL = 6.0 mA IOH = - 2.0 mA IOH = - 4.0 mA IOH = - 6.0 mA VIN = VDD or VSS VIN = VDD VIN = VSS VDD = Max, VOUT = VSS or VDD VDD = Max, VOUT = VSS VDD = Max, VOUT = VDD VIN = VDD or VSS = 0 mA VIN = VIH or VIL = 27 MHz Condition1 Min Typ Max Units - - - - 0.8 0.2 VDD - - 5.5 0.4 0.4 0.4 - - - + 10 222 - 35 + 10 - 40 140 10 215 V V VIH 2.0 0.7 VDD 2.0 - - - 2.4 2.4 2.4 - 10 35 - 214 - 10 - 117 37 10 215 - - - 0.2 0.2 0.2 - - - 10 115 - 115 1 - 75 90 10 215 V V V V V V V V V A A A A mA mA mA mA VOL VOH IIL IOZ IOSP4 IOSN4 IDD IDD 1. 2. 3. 4. Specified at VDD equals 3.3 V 5% at ambient temperature over the specified range. For CMOS and TLL inputs. Not more than one output may be shorted at a time for a maximum duration of one second. These values scale proportionally for output buffers with different drive strengths. 54 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Table 17 Pin Description Summary Drive (mA) 6 6 4 8 8 8 - 8 - 6 6 6 6 - 2 - 8 6 6 6 Pull-Up/ Down - - - - - U3 - - Mnemonic ACKn/ AUXNM ACLK AD[31:0] ADDR[7:0] AD[15:0] AREQn ALE AUTOFDn/ AUXV GPIO14 AVALID AVD[7:0] AVDD AVERRn AVSS BEn[1:0] BEn[3:2] GPIO[3:2] BUSY/ AUXSB GPIO15 CCLK CDATA[7:0] CERRn CPU_CLK CSn[3:0] Description 1284 Acknowledge Aux No Match Audio Clock EBus Address/Data EBus Address/Data EBus Address/Data Audio Data Request EBus Address Latch Enable 1284 Auto Feed Aux Data Valid General-Purpose IO 14 Audio Data Valid Audio/Video Data Analog Power Audio/Video Error Analog Ground EBus Byte Enable EBus Byte Enable 1284 Busy Aux Sync Byte General-Purpose IO 15 Channel Data Clock Channel Data Channel Data Error EBus Clock Output EBus Chip Select Type1 Output Output Output Bidirectional Bidirectional Bidirectional Input Output Input Bidirectional Bidirectional Output Bidirectional Input Output Input Bidirectional Output Bidirectional Bidirectional Active2 LOW HIGH - - - - LOW LOW LOW HIGH - - LOW - LOW LOW LOW - - - - - - - - Input Input Input Output Output - - - 6 8 - - LOW LOW LOW - - U - - L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 55 Table 17 Pin Description Summary (Cont.) Type1 Output Bidirectional Output Input Bidirectional Input Input Input Bidirectional Output Bidirectional Input Input Bidirectional Drive (mA) 6 6 6 - 6 - - - 6 6 6 - - 6 Active2 LOW LOW LOW LOW HIGH LOW LOW LOW - LOW Pull-Up/ Down - - U U D4 U - U - - Mnemonic CSn[4] GPIO1 CSn[5] / MEMSTBn CTSn0 GPIO7 CTSn1 ICECLK CVALID DSRn0 GPIO9 DTRn0 GPIO8 EACKn ECLK FAULTn/ AUXCLK GPIO24 GPIO[42:43] GPIO[46:45] GPIO[48:49] IDDTN INITn/ AUXPID[2] GPIO25 INTn[3:0] INTn4 IRBL GPIO47 Description EBus Chip Select General-Purpose IO 1 EBus Chip Select Memory Strobe Clear To Send (SIO 0) General-Purpose I/O 7 Clear To Send (SIO 1) Serial ICE Clock Channel Data Enable Data Send Ready (SIO 0) General-Purpose I/O 9 Data Terminal Ready (SIO 0) General-Purpose I/O 8 EBus Data Acknowledge PLL Test Clock 1284 Fault Aux Port Clock General-Purpose I/O 24 General-Purpose I/O General-Purpose I/O General-Purpose I/O Test Pin 1284 Initialization Aux Packet ID 2 General-Purpose I/O 25 Interrupt Interrupt IR Blaster General-Purpose I/O 47 Bidirectional Bidirectional Bidirectional Input Input Output Bidirectional Input Bidirectional (open drain) Output Bidirectional 4 4 4 - - 6 6 - 6 4 4 - - - HIGH LOW - U - - - LOW LOW HIGH U - - 56 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Table 17 Pin Description Summary (Cont.) Drive (mA) - - 4 - 4 4 4 - 4 6 - 6 6 6 - - 4 8 - Pull-Up/ Down - - - - - - - - Mnemonic IREF IRRX0 GPIO40 IRRX1 GPIO41 IRTX GPIO44 OP_MODE[1:0] PDATA[7:0] PDATA_DIR / OP_MODE[2] PERROR/ AUXPID[0] GPIO26 PLLVDD PLLVSS RCLK RDn RESETn Description Current Reference IR Receiver Port 0 General-Purpose I/O 40 IR Receiver Port 1 General-Purpose I/O 41 IR Transmitter Port General-Purpose I/O 44 Operational Mode 1284 Data 1284 Data Direction or Operational Mode[2] 1284 Peripheral Error Aux Packet ID [0] General-Purpose I/O 26 PLL Analog VDD PLL Analog VSS UART Receive Clock (SIO 0) EBus Read Strobe Reset Type1 - Input Bidirectional Input Bidirectional Output Bidirectional Input Bidirectional Output Input Output Output Bidirectional Input Input Input Output Input (Schmitt trigger) Output Bidirectional Output Input Bidirectional Input Input Output Active2 - - - - - - - HIGH - - - LOW LOW - - - U U RTSn0 GPIO10 RTSn1 RXD0 GPIO11 RXD1/ ICE_RX RXD2 SA[11:0] Request To Send (SIO 0) General-Purpose I/O 10 Request To Send (SIO 1) Receive Data (SIO 0) General-Purpose I/O 11 Receive Data (SIO 1) Receive Data Serial ICE Port Receive Data (SIO 2) SDRAM Address Bus 6 6 6 - 6 4 - 6 LOW LOW - - - - - - U U U - L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 57 Table 17 Pin Description Summary (Cont.) Type1 Output Output Bidirectional Bidirectional (open drain) Bidirectional (open drain) Output Bidirectional Input Bidirectional Bidirectional (open drain) Output Bidirectional Output Bidirectional Output Bidirectional Output Bidirectional Input Bidirectional Bidirectional (open drain) Output Bidirectional Output Bidirectional Output Bidirectional Drive (mA) 6 6 6 6 6 6 6 4 6 4 4 4 4 4 4 6 6 - 4 6 4 4 4 4 4 4 Active2 - - - - - - HIGH - LOW LOW LOW - HIGH - LOW LOW LOW Pull-Up/ Down - - - - - - - - - - - - - - - - - Mnemonic SBA[0] SBA[1] SBD[15:0] SC0_C4 SC0_C8 SC0_CLK GPIO33 SC0_DETECT GPIO31 SC0_I/O SC0_RSTn GPIO30 SC0_VCC_ENn GPIO32 SC0_VPP_ENn GPIO34 SC1_CLK GPIO38 SC1_DETECT GPIO36 SC1_I/O SC1_RSTn GPIO35 SC1_VCC_ENn GPIO37 SC1_VPP_ENn GPIO39 Description SDRAM Bank Select 0 SDRAM Bank Select 1 SDRAM Data Bus SmartCard 0 C4 SmartCard 0 C8 SmartCard 0 Clock General-Purpose I/O 33 SmartCard 0 Detect General-Purpose I/O 31 SmartCard 0 Data SmartCard 0 Reset General-Purpose I/O 30 SmartCard 0 VCC Enable General-Purpose I/O 32 SmartCard 0 VPP Enable General-Purpose I/O 34 SmartCard 1 Clock General-Purpose I/O 38 SmartCard 1 Detect General-Purpose I/O 36 SmartCard 1 Data SmartCard 1 Reset General-Purpose I/O 35 SmartCard 1 VCC Enable General-Purpose I/O 37 SmartCard 1 VPP Enable General-Purpose I/O 39 58 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Table 17 Pin Description Summary (Cont.) Drive (mA) 8 8 - 8 6 6 8 8 4 6 6 6 - 6 - 6 4 - - 4 6 8 - - 4 - Pull-Up/ Down - - - - - D - - - Mnemonic SCASn SCL SCLK SDA SDCLK SDET SDQMH GPIO6 SDQML SELECT/ AUXPID[1] GPIO27 SELECTINn/ AUX_ADP/ AUX_ERR GPIO28 SRASn STROBEn/ AUX_TX GPIO29 SWEn TCLK TCK TDI TDO TMS Description SDRAM Column Address Strobe I2C Clock System Clock (27 MHz) I2C Data SDRAM Master Clock Sigma-Delta Control Voltage Output SDRAM Data Mask High Byte General-Purpose I/O 6 SDRAM Data Mask Low Byte 1284 Selection Aux Packet ID [1] 1284 Selection Indicator Aux Adaptation Field Flag Aux Error Indicator General-Purpose I/O 28 SDRAM Row Address Strobe 1284 Data Strobe Aux Port Direction General-Purpose I/O 29 SDRAM Write Enable UART Transmit Clock (SIO 0) JTAG Scan Clock JTAG Scan In JTAG Scan Out JTAG Mode Type1 Output Bidirectional (open drain) Input Bidirectional (open drain) Output Output (open drain) Output Bidirectional Output Output Output Bidirectional Input Output Input Bidirectional Output Input Input Bidirectional Output Input Input Input Output (3-State) Input Active2 LOW - - - - - HIGH - LOW LOW - LOW LOW - - LOW LOW - - - - - U - - - - L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 59 Table 17 Pin Description Summary (Cont.) Type1 Input Output Bidirectional Input Bidirectional Output Output Output - Input - Output Output Input Drive (mA) - 6 6 - 6 6 6 6 - - - 6 8 - Active2 HIGH - HIGH - - - - LOW - HIGH LOW LOW Pull-Up/ Down D U D - - - - U - - U U Mnemonic TRST TTXDATA GPIO13 TTXREQ GPIO12 TXD0 TXD1 ICE_TX TXD2 VDD VREQn VSS VVALID WRn ZTESTn 1. 2. 3. 4. Description JTAG Reset Teletext Data General-Purpose I/O 13 Teletext Request General-Purpose I/O 12 Transmit Data (SIO 0) Transmit Data (SIO 1) Transmit Data Serial ICEPort Transmit Data (SIO 2) Power Video Data Request Ground Video Data Valid EBus Write Strobe Test Pin If only one pin type is listed, it applies to all possible pin configurations. If only active state (LOW or HIGH) is listed, it applies to all possible pin configurations. The internal pull-up resistor value is from 50-100 k The internal pull-down resistor value is from 50-100 k 60 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Packaging and Pinouts Figure 6 shows the signal solder balls of the L64118. This diagram shows the location, ball number, and signal for each solder ball on the 256-pin Plastic Ball Grid Array (PBGA) package (package code IF). This pinout drawing is followed by: * * * a listing of the solder balls in numerical order for the L64118 (Table 18) a listing of the solder balls in alphabetic order for the L64118 (Table 19) mechanical drawings that provide the dimensions of the L64118 (Figure 7) Note: All drawings in this section use the same origin. In other words, solder ball A1 in Figure 6 and Figure 7 are the same. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 61 62 D IRTX GPIO48 NC IRRX1 TXD2 AVD[7] TDO AVD[1] NC NC NC TRST SDET AVD[6] AVD[5] AVD[3] TDI RXD2 NC NC IRBL GPIO45/ CDATA[0] CDATA[4] RCLK OP_ MODE[1] AVD[0] AVALID VREQn NC NC SC0_ RSTn SC0_ CLK SC1_ RSTn SC1_ VCC_ ENn SC1_CLK AD[14] AD[13] SC0_ DETECT SC0_C4 SC0_VPP_ AVERRn ENn E F G H J K L M N P R T U V W Y GPIO42 CERRn CDATA[6] CDATA[7] CDATA[1] CDATA[5] NC ECLK CDATA[3] CDATA[2] GPIO46 GPIO49 SCLK TCK TMS AVD[2] VSS CVALID VDD CCLK VSS IDDTN VDD AVD[4] VSS VVALID VDD AREQn PLLVSS OP_ MODE[0] VSS SC0_IO SC0_ VCC_ ENn VDD SC1_ VPP_ ENn SC0_C8 SC1_ DETECT AD[15] VDD SA[0] VSS SC1_IO AD[12] VSS AD[11] AD[10] AD[9] SA[10] AD[8] AD[7] AD[6] AD[5] A B C Figure 6 1 VSS ACLK GPIO43 2 NC NC IRRX0 3 PLLVDD NC NC 4 IREF AVDD NC 5 SA[1] ZTESTn AVSS 6 SA[4] SA[2] SDCLK 7 SA[6] SA[5] SA[3] 8 SA[9] SA[8] SA[7] 9 SRASn SBA[1] SBA[0] SA[11] L64118 256-Pin PBGA Pinout 10 SDQMH SWEn SCASn VDD AD[3] AD[4] AD[2] 11 SDQML SBD[14] SBD[15] VDD ADDR[1] ADDR[0] ADDR[5] ADDR[4] AD[0] ADDR[3] AD[1] ADDR[2] 12 SBD[13] SBD[12] SBD[11] SBD[10] 13 SBD[9] SBD[8] SBD[7] VSS VSS AD[16] ADDR[7] ADDR[6] 14 SBD[6] SBD[5] SBD[4] SBD[1] AD[23] AD[20] AD[18] AD[17] 15 SBD[3] SBD[2] SBD[0] VDD VDD AD[24] AD[21] AD[19] 16 VSS RXD1 VDD PERROR VSS TTXREQ TTXDATA DSRn0 TXD0 AD[29] AD[27] AD[25] AD[22] 17 NC NC SELECT PDATA[0] PDATA[4] CTSn0 DTRn0 NC PDATA[7] STROBEn VDD CSn2 VSS CPU_CLK VDD AD[30] VSS NC NC AD[26] 18 NC FAULTn ACKn PDATA[2] PDATA[5] NC TCLK NC SELECTINn INITn SDA INTn2 CSn1 CSn5/ MEMSTBn SCL INTn1 CSn0 CSn4 BEn2 WRn EACKn NC NC NC AD[28] 19 RTSn0 CTSn1 NC BEn3 BEn0 ALE NC NC NC NC L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) TXD1 BUSY PDATA[1] PDATA[3] PDATA[6] AUTOFDn INTn4 INTn3 INTn0 CSn3 RESETn BEn1 RDn AD[31] 20 RXD0 PDATA_ DIR/OP_ MODE[2] RTSn1 NC NC NC Table 18 Solder Ball L64118 Solder Ball Matrix List Signal Solder Ball P3 R3 T3 U3 V3 W3 Y3 A4 B4 C4 D4 E4 F4 G4 H4 J4 K4 L4 M4 N4 P4 R4 T4 U4 V4 W4 Y4 A5 B5 C5 D5 U5 V5 W5 Y5 A6 B6 C6 D6 U6 V6 W6 Y6 A7 B7 C7 D7 U7 V7 W7 Y7 A8 B8 Signal Solder Signal Ball C8 D8 U8 V8 W8 Y8 A9 B9 C9 D9 U9 V9 W9 Y9 A10 B10 C10 D10 U10 V10 W10 Y10 A11 B11 C11 D11 U11 V11 W11 Y11 A12 B12 C12 C12 U12 V12 W12 Y12 A13 B13 C13 D13 U13 V13 W13 Y13 A14 B14 C14 D14 U14 V14 W14 SA[7] VSS VSS AD[11] AD[10] AD[9] SBA[1] SBA[0] SA[11] SA[10] AD[8] AD[7] AD[6] AD[5] SDQMH SWEn SCASn SRASn VDD AD[3] AD[4] AD[2] SDQML SBD[14] SBD[15] VDD ADDR[1] ADDR[0] AD[0] AD[1] SBD[13] SBD[12] SBD[11] SBD[10] ADDR[5] ADDR[4] ADDR[3] ADDR[2] SBD[9] SBD[8] SBD[7] VSS VSS AD[16] ADDR[7] ADDR[6] SBD[6] SBD[5] SBD[4] SBD[1] AD[23] AD[20] AD[18] Solder Ball Signal Solder Signal Ball U18 NC V18 NC W18 NC Y18 AD[28] A19 RTSn0 B19 CTSn1 C19 NC D19 NC E19 FAULTn F19 ACKn G19 PDATA[2] H19 PDATA[5] J19 INITn K19 SCL L19 INTn1 M19 CSn0 N19 CSn4 P19 BEn3 R19 BEn0 T19 ALE U19 NC V19 NC W19 NC Y19 NC A20 RXD0 B20 PDATA_DIR/ OP_MODE[2] C20 RTSn1 D20 TXD1 E20 BUSY F20 PDATA[1] G20 PDATA[3] H20 PDATA[6] J20 AUTOFDn K20 INTn4 L20 INTn3 M20 INTn0 N20 CSn3 P20 RESETn R20 BEn1 T20 RDn U20 AD[31] V20 NC W20 NC Y20 NC A1 VSS B1 ACLK C1 GPIO43 D1 IRTX E1 IRBL F1 GPIO48 G1 GPIO45/RCLK H1 CDATA[0] J1 CDATA[4] K1 TRST L1 SDET M1 AVD[6] N1 AVD[5] P1 AVD[3] R1 TDI T1 RXD2 U1 NC V1 NC W1 AVERRn Y1 SC0_VPP_ENn A2 NC B2 NC C2 IRRX0 D2 GPIO42 E2 CERRn F2 CDATA[6] G2 CDATA[7] H2 CDATA[1] J2 CDATA[5] K2 NC L2 TXD2 M2 AVD[7] N2 TDO P2 OP_MODE[1] R2 AVD[1] T2 IRRX1 U2 NC V2 NC W2 NC Y2 SC0_DETECT A3 PLLVDD B3 NC C3 NC D3 NC E3 ECLK F3 CDATA[3] G3 CDATA[2] H3 GPIO46 J3 GPIO49 K3 SCLK L3 TCK M3 TMS N3 AVD[2] AVD[0] AVALID VREQn NC NC SC0_RSTn SC0_C4 IREF AVDD NC VSS CVALID VDD CCLK VSS IDDTN VDD OP_MODE[0] AVD[4] VSS VVALID VDD AREQn VSS SC0_IO SC0_CLK SC0_C8 SA[1] ZTESTn AVSS PLLVSS SC0_VCC_ENn SC1_VPP_ENn SC1_RSTn SC1_DETECT SA[4] SA[2] SDCLK VDD VDD SC1_CLK SC1_VCC_ENn AD[15] SA[6] SA[5] SA[3] SA[0] SC1_IO AD[14] AD[13] AD[12] SA[9] SA[8] Y14 AD[17] A15 SBD[3] B15 SBD[2] C15 SBD[0] D15 VDD U15 VDD V15 AD[24] W15 AD[21] Y15 AD[19] A16 TTXREQ B16 TTXDATA C16 DSRn0 D16 TXD0 U16 AD[29] V16 AD[27] W16 AD[25] Y16 AD[22] A17 CTSn0 B17 DTRn0 C17 NC D17 VSS E17 RXD1 F17 VDD G17 PERROR H17 VSS J17 PDATA[7] K17 STROBEn L17 VDD M17 CSn2 N17 VSS P17 CPU_CLK R17 VDD T17 AD[30] U17 VSS V17 NC W17 NC Y17 AD[26] A18 NC B18 TCLK C18 NC D18 NC E18 NC F18 SELECT G18 PDATA[0] H18 PDATA[4] J18 SELECTINn K18 SDA L18 INTn2 M18 CSn1 N18 CSn5/MEMSTBn P18 BEn2 R18 WRn T18 EACKn L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 63 Table 19 Signal ACKn ACLK AD[0] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[1] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[2] AD[30] AD[31] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] ADDR[0] ADDR[1] ADDR[2] ADDR[3] ADDR[4] ADDR[5] ADDR[6] ADDR[7] ALE AREQn AUTOFDn AVALID AVD[0] AVD[1] AVD[2] AVD[3] AVD[4] AVD[5] AVD[6] L64118 Alphabetical Signal List Solder Ball F19 B1 W11 W8 V8 Y7 W7 V7 Y6 V13 Y14 W14 Y15 Y11 V14 W15 Y16 U14 V15 W16 Y17 V16 Y18 U16 Y10 T17 U20 V10 W10 Y9 W9 V9 U9 Y8 V11 U11 Y12 W12 V12 U12 Y13 W13 T19 T4 J20 R3 P3 R2 N3 P1 M4 N1 M1 Signal Solder Ball M2 B4 W1 C5 R19 R20 P18 P19 E20 G4 H1 H2 G3 F3 J1 J2 F2 G2 E2 P17 M19 M18 M17 N20 N19 N18 A17 B19 E4 C16 B17 T18 E3 E19 D2 C1 G1 H3 F1 J3 J4 J19 M20 L19 L18 L20 K20 E1 A4 C2 T2 D1 U1 Signal Solder Ball V1 A2 B2 K2 U2 V2 W2 B3 C3 D3 U3 V3 C4 C17 V17 W17 A18 C18 D18 E18 U18 V18 W18 C19 D19 U19 V19 W19 Y19 V20 W20 Y20 L4 P2 G18 F20 G19 G20 H18 H19 H20 J17 B20 G17 A3 D5 T20 P20 A19 C20 A20 E17 Signal Solder Signal Ball T1 D7 D9 C9 A5 B6 C7 A6 B7 A7 C8 B8 A8 B9 A9 C15 C12 C12 B12 A12 B11 C11 D14 B15 A15 C14 B14 A14 C13 B13 A13 Y3 Y4 W4 Y2 V4 W3 U5 Y1 V6 Y5 U7 W5 W6 V5 C10 K19 K3 K18 C6 L1 A10 A11 Solder Ball F18 J18 D10 K17 B10 L3 B18 R1 N2 M3 K1 B16 A16 D16 D20 L2 F4 K4 R4 D6 U6 U10 D11 D15 U15 F17 L17 R17 T3 A1 D4 H4 N4 U4 D8 U8 D13 U13 D17 H17 N17 U17 P4 R18 B5 AVD[7] AVDD AVERRn AVSS BEn0 BEn1 BEn2 BEn3 BUSY CCLK CDATA[0] CDATA[1] CDATA[2] CDATA[3] CDATA[4] CDATA[5] CDATA[6] CDATA[7] CERRn CPU_CLK CSn0 CSn1 CSn2 CSn3 CSn4 CSn5/MEMSTBn CTSn0 CTSn1 CVALID DSRn0 DTRn0 EACKn ECLK FAULTn GPIO42 GPIO43 GPIO45/RCLK GPIO46 GPIO48 GPIO49 IDDTN INITn INTn0 INTn1 INTn2 INTn3 INTn4 IRBL IREF IRRX0 IRRX1 IRTX NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC OP_MODE[0] OP_MODE[1] PDATA[0] PDATA[1] PDATA[2] PDATA[3] PDATA[4] PDATA[5] PDATA[6] PDATA[7] PDATA_DIR/ OP_MODE[2] PERROR PLLVDD PLLVSS RDn RESETn RTSn0 RTSn1 RXD0 RXD1 RXD2 SA[0] SA[10] SA[11] SA[1] SA[2] SA[3] SA[4] SA[5] SA[6] SA[7] SA[8] SA[9] SBA[0] SBA[1] SBD[0] SBD[10] SBD[11] SBD[12] SBD[13] SBD[14] SBD[15] SBD[1] SBD[2] SBD[3] SBD[4] SBD[5] SBD[6] SBD[7] SBD[8] SBD[9] SC0_C4 SC0_C8 SC0_CLK SC0_DETECT SC0_IO SC0_RSTn SC0_VCC_ENn SC0_VPP_ENn SC1_CLK SC1_DETECT SC1_IO SC1_RSTn SC1_VCC_ENn SC1_VPP_ENn SCASn SCL SCLK SDA SDCLK SDET SDQMH SDQML SELECT SELECTINn SRASn STROBEn SWEn TCK TCLK TDI TDO TMS TRST TTXDATA TTXREQ TXD0 TXD1 TXD2 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VREQn VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VVALID WRn ZTESTn 64 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Figure 7. 256-Pin PBGA Package (IF) Mechanical Drawing MD98.IF Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code IF. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 65 Notes 66 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Notes L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 67 Sales Offices and Design Resource Centers LSI Logic Corporation Corporate Headquarters Tel: 408.433.8000 Fax: 408.433.8989 NORTH AMERICA California Irvine Tel: 714.553.5600 Fax: 714.474.8101 San Diego Tel: 619.613.8300 Fax: 619.613.8350 Wireless Design Center Tel: 619.350.5560 Fax: 619.350.0171 New York New York Tel: 716.223.8820 Fax: 716.223.8822 North Carolina Raleigh Tel: 919.785.4520 Fax: 919.783.8909 Oregon Beaverton Tel: 503.645.0589 Fax: 503.645.6612 Texas Austin Tel: 512.388.7294 Fax: 512.388.4171 Denmark Ballerup LSI Logic Development Centre Tel: 45.44.86.55.55 Fax: 45.44.86.55.56 France Paris LSI Logic S.A. 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As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified the functional descriptions or electrical and mechanical specifications using production parts. LSI Logic logo design, G10, and CoreWare are registered trademarks and TinyRISC is a trademark of LSI Logic Corporation. All other brand and product names may be trademarks of their respective companies. Printed in USA Order No. I15038 Doc. No. DB08-000109-01 LSI Logic Corporation reserves the right to make changes to any products and services herein at any time without notice. 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